Hardened at the Core.
Autonomous in the Field.
The iPU architecture delivers silicon-layer immunity and self-adapting logic for mission-critical systems operating in contested, disconnected, or resource-constrained environments—perfect for ISR, autonomy, and cyber-electronic warfare resilience.
DARPA iPU Phase 2 Innovation Summary
AdaptMicroSys is advancing a secure post-von Neumann processing architecture under DARPA Phase 2.
The following table summarizes the core innovations of our iPU (Immunized Processing Unit) and their impact across national security, AI acceleration, and edge computing.
Securing the Future: DARPA iPU Phase 2 Progress & Innovations
Phase 2 of the DARPA iPU (Immunized Processing Unit) program marks a major leap in secure, adaptive microprocessor design—targeting mission-critical resilience, real-time threat mitigation, and autonomy at the silicon layer.
DARPA iPU Phase 2
Innovation Summary
Phase 2 of the DARPA iPU (Immunized Processing Unit) program represents a pivotal advancement in the development of secure, adaptive, and mission-critical microprocessor architecture. Building upon foundational research from Phase 1, this phase integrates new defense-grade capabilities across hardware, software, and architectural layers—designed specifically to meet the needs of dynamic, high-threat operational environments.
At the core of Phase 2 innovations is the deployment of the Immunized Processing Unit Core, featuring embedded, silicon-level threat detection and response mechanisms that enable continuous, autonomous mitigation of runtime anomalies. These capabilities empower AI-driven systems to operate securely and reliably, even in contested domains where traditional security models fail.
A major breakthrough introduced in Phase 2 is Machine Language Hopping (MLH)—a moving target defense strategy that dynamically reconfigures machine-level instruction sets during runtime. This technique significantly raises the bar for adversarial reverse engineering, injection attacks, and persistent threat persistence by ensuring that the processor's execution environment is never static or predictable.
| Innovation Area | Description | Impact |
|---|---|---|
| Immunized Processing Unit Core | Core-level threat detection and response mechanisms embedded in silicon. | Enables real-time anomaly mitigation and secure execution in contested environments. |
| Machine Language Hopping (MLH) | Dynamic switching of machine instruction sets during runtime to create a moving-target defense. | Increases resistance to reverse engineering, code injection, and persistent threats. |
| Pipeline Security Design | Hardened execution model with runtime validation, speculative execution monitoring, and secure branch handling. | Protects against microarchitectural attacks while maintaining high performance. |
| Hardware-Software Co-Design | Adaptive integration between programmable hardware logic and intelligent software layers. | Enables secure orchestration, power optimization, and mission-aware compute adaptation. |